Pipeline processor with prefetch circuit
US5148532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1990 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Nov 7, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/264
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instruction decoder to generate micro-addresses which address is a micro-ROM. The first micro-instruction retrieved from the micro-ROM contains information for executing a conditional discrimination, a signal requesting branch ready, and a subsequent micro-address for the actual execution of the branch request in accordance with the result of the conditional discrimination. When the branch condition is satisfied, a micro-address generating circuit feeds the subsequent micro-instruction to a micro-ROM address decoder and the least significant bit of the subsequent micro-address to a micro-address analyzing circuit. The branch ready information of the first micro-instruction is also fed to the micro-address analyzing circuit to prefetch a target branch macro-instruction from an associated memory before the micro-ROM outputs the micro-instruction, corresponding to the subsequent micro-address, t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.