Fermi threshold silicon-on-insulator field effect transistor
US5151759A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1991 |
| Grant date | Sep 29, 1992 |
| Priority date | — |
| Expiry date | Jan 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
Abstract
A Silicon-on-Insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.