Semiconductor memory including an arrangement to permit external monitoring of an internal control signal
US5151881A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1988 |
| Grant date | Sep 29, 1992 |
| Priority date | — |
| Expiry date | Apr 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory comprises a memory array including a plurality of memory cells, a peripheral circuit which executes either an information write or read operation with respect to one or more memory cells selected from the plurality of memory cells, a timing control circuit which forms at least one internal control signal for controlling the peripheral circuit, and at least one external terminal for delivering said at least one internal control signal to the outside of the semiconductor memory. For example, the peripheral circuit can include an arrangement to permit the peripheral circuit to operate in a test mode to deliver the internal control signal to the external terminal to allow external testing of the operation of the internal control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.