Memory integrated circuit test mode switching
US5155704A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1990 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Oct 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An external test mode enable signal (xTE) applied to a memory IC is filtered on board the memory IC to prevent inadvertent switching into test mode due to noise. In one approach, the test mode enable signal passes through an internal RC low-pass filter (18,20) to reject high frequency signals. Another approach is filtering the enable signal digitally using an xRAS* signal as a filter signal. Logic (FIG. 2) is provided to assert test mode (node C) only when the external enable signal has been asserted for at least a minimum time determined by the filter signal, again to avoid false switching. Either approach allows lowering test mode enable signal voltages below those used presently. The invention, therefore, can be used with particular advantage to maintain test mode enable noise margin in small geometry circuits which cannot withstand supervoltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.