Pipelined apparatus and method for controlled loading of floating point data in a microprocessor
US5155816A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Aug 8, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.