Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
US5156986A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1991 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Mar 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.