Fabricating a memory cell with an improved capacitor
US5156993A · kind A · utility
24Cited by
2References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 17, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Aug 17, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A process for producing a random access memory cell having an improved capacitor structure that thereby permits greater integration. The capacitor is a merged combination of a stacked trench and a stacked capacitor which has at least two plates separated by a dielectric layer. The plates are formed of polysilicon and extend partially over the gate region, over the source region, over the sidewalls and bottom of a trench, and partially over the field oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.