Master-slave checking system
US5157780A · kind A · utility
30Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Jun 12, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.