Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation
US5158901A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1991 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Sep 30, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.