Tri-state bus driver to support reconfigurable fault tolerant logic
US5159273A · kind A · utility
43Cited by
2References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | Oct 27, 1992 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-state driver circuit including a first gating circuit responsive to a first enable signal for selectively gating an input signal to provide a first gated signal at an internal node, a second gating means responsive to a second enable signal and connected to the internal node for selectively gating the first gated signal so as to provide the output of the three-state bus driver, and a testing circuit for detecting or controlling the state of the internal node, and for providing a test output indicative of the inoperability of the first or second gating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.