Jeffrey P. Wright
140Patents
26h-index
61Co-inventors
93Inventor score
Filing activity: Sep 28, 1990 → Jul 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5627791A | Multiple bank memory with auto refresh to specified bank | Physics | 236 | Expired |
| US5959929A | Method for writing to multiple banks of a memory device | Physics | 96 | Expired |
| US6665222B2 | Synchronous dynamic random access memory device | Physics | 81 | Expired |
| US6172935A | Synchronous dynamic random access memory device | Physics | 79 | Expired |
| US6365421B2 | Method and apparatus for storage of test results within an integrated circuit | Physics | 73 | Expired |
| US9741409B2 | Apparatuses and methods for targeted refreshing of memory | Physics | 72 | Active |
| US9324398B2 | Apparatuses and methods for targeted refreshing of memory | Physics | 72 | Active |
| US10147472B2 | Apparatuses and methods for targeted refreshing of memory | Physics | 70 | Active |
| US6194738A | Method and apparatus for storage of test results within an integrated circuit | Physics | 67 | Expired |
| US5673233A | Synchronous memory allowing early read command in write to read transitions | Physics | 55 | Expired |
| US5903509A | Memory device with multiple internal banks and staggered command execution | Physics | 48 | Expired |
| US5966388A | High-speed test system for a memory device | Physics | 48 | Expired |
| US5999481A | Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals | Physics | 44 | Expired |
| US5159273A | Tri-state bus driver to support reconfigurable fault tolerant logic | Physics | 43 | Expired |
| US6154860A | High-speed test system for a memory device | Physics | 42 | Expired |
| US5895962A | Structure and a method for storing information in a semiconductor device | Electricity | 41 | Expired |
| US5748551A | Memory device with multiple internal banks and staggered command execution | Physics | 39 | Expired |
| US5883853A | Clock frequency detector for a synchronous memory device | Physics | 36 | Expired |
| US5805505A | Circuit and method for converting a pair of input signals into a level-limited output signal | Electricity | 34 | Expired |
| US5587961A | Synchronous memory allowing early read command in write to read transitions | Physics | 33 | Expired |
| US6190972A | Method for storing information in a semiconductor device | Electricity | 32 | Expired |
| US10861519B2 | Apparatuses and methods for targeted refreshing of memory | Physics | 31 | Active |
| US6550026B1 | High speed test system for a memory device | Physics | 30 | Expired |
| US6049502A | Method for writing to multiple banks of a memory device | Physics | 29 | Expired |
| US6104651A | Testing parameters of an electronic device | Physics | 27 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.