Sense amplifier with depletion transistor feedback
US5162679A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1991 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | May 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit is disclosed which utilizes a field effect transistor having a negative threshold voltage to provide a faster switching speed for a given current consumption. A depletion mode transistor is utilized as the feedback transistor, with the gate of the depletion mode transistor being coupled to the output of the second stage of the sense amplifier. The first stage of the sense amplifier includes in addition to the depletion mode transistor a second field effect transistor connected in series with said feedback transistor, with the gate and drain of the second transistor being commonly connected. The sense amplifier circuit also includes third and fourth stages providing inversion and amplification of the signal provided at the output of the second stage, with the third and fourth stages comprising a depletion load inverter and a CMOS inverter, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.