Ju Shen
54Patents
21h-index
41Co-inventors
88Inventor score
Filing activity: Aug 15, 1989 → Aug 27, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5233539A | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Electricity | 185 | Expired |
| US5422823A | Programmable gate array device having cascaded means for function definition | Electricity | 164 | Expired |
| US5586044A | Array of configurable logic blocks including cascadable lookup tables | Electricity | 95 | Expired |
| US5587921A | Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer | Electricity | 92 | Expired |
| US5336951A | Structure and method for multiplexing pins for in-system programming | Physics | 91 | Expired |
| US6828823B1 | Non-volatile and reconfigurable programmable logic devices | Electricity | 87 | Expired |
| US5212652A | Programmable gate array with improved interconnect structure | Electricity | 86 | Expired |
| US5260881A | Programmable gate array with improved configurable logic block | Electricity | 81 | Expired |
| US5237218A | Structure and method for multiplexing pins for in-system programming | Physics | 77 | Expired |
| US5329460A | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Electricity | 73 | Expired |
| US5412260A | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device | Electricity | 66 | Expired |
| US6356107B1 | Method and structure dynamic in-system programming | Electricity | 51 | Expired |
| US6304099A | Method and structure for dynamic in-system programming | Electricity | 50 | Expired |
| US5740069A | Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs) | Electricity | 46 | Expired |
| US5394033A | Structure and method for implementing hierarchical routing pools in a programmable logic circuit | Electricity | 42 | Expired |
| US5359536A | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Electricity | 40 | Expired |
| US6229336A | Programmable integrated circuit device with slew control and skew control | Electricity | 40 | Expired |
| US5191243A | Output logic macrocell with enhanced functional capabilities | Electricity | 34 | Expired |
| US5598346A | Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks | Electricity | 29 | Expired |
| US7675313B1 | Methods and systems for storing a security key using programmable fuses | Physics | 27 | Active |
| US5490074A | Constant delay interconnect for coupling configurable logic blocks | Electricity | 23 | Expired |
| US7375549B1 | Reconfiguration of programmable logic devices | Electricity | 20 | Active |
| US6765408B2 | Device and method with generic logic blocks | Electricity | 19 | Expired |
| US5130574A | Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device | Electricity | 17 | Expired |
| US6777979B1 | FIFO memory architecture | Electricity | 17 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.