Enhanced locked bus cycle control in a cache memory computer system
US5163143A · kind A · utility
22Cited by
8References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 3, 1990 |
| Grant date | Nov 10, 1992 |
| Priority date | — |
| Expiry date | Nov 3, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controlled 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.