Mark Taylor
30Patents
15h-index
49Co-inventors
81Inventor score
Filing activity: Sep 28, 1987 → Jan 7, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5737604A | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | Physics | 123 | Expired |
| US5966304A | Redundant automation controller permitting replacement of components during operation | Physics | 76 | Expired |
| US5963448A | Industrial controller having redundancy and using connected messaging and connection identifiers to enable rapid switchover without requiring new connections to be opened or closed at switchover | Physics | 67 | Expired |
| US6125449A | Controlling power states of a computer | Physics | 57 | Expired |
| US5535395A | Prioritization of microprocessors in multiprocessor computer systems | Physics | 54 | Expired |
| US5553310A | Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems | Physics | 49 | Expired |
| US5966301A | Redundant processor controller providing upgrade recovery | Physics | 45 | Expired |
| US5303364A | Paged memory controller | Physics | 39 | Expired |
| US5519839A | Double buffering operations between the memory bus and the expansion bus of a computer system | Physics | 29 | Expired |
| US5870568A | Double buffering operations between the memory bus and the expansion bus of a computer system | Physics | 27 | Expired |
| US6076133A | Computer interface with hardwire button array | Electricity | 26 | Expired |
| US5163143A | Enhanced locked bus cycle control in a cache memory computer system | Physics | 22 | Expired |
| US5465360A | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | Physics | 20 | Expired |
| US5966300A | Redundant automation controller with deductive power-up | Physics | 17 | Expired |
| US5134713A | Coprocessor detection circuit | Physics | 16 | Expired |
| US5870602A | Multi-processor system with system wide reset and partial system reset capabilities | Physics | 15 | Expired |
| US5253358A | Cache memory expansion and transparent interconnection | Physics | 14 | Expired |
| US6018620A | Double buffering operations between the memory bus and the expansion bus of a computer system | Physics | 14 | Expired |
| US4807266A | Circuit and method for performing equal duty cycle odd value clock division and clock synchronization | Electricity | 13 | Expired |
| US5987537A | Function selector with external hard wired button array on computer chassis that generates interrupt to system processor | Physics | 8 | Expired |
| US7680900B2 | Publish/subscribe messaging system | Electricity | 7 | Active |
| US5751998A | Memory accessing system with portions of memory being selectively write protectable and relocatable based on predefined register bits and memory selection RAM outputs | Physics | 6 | Expired |
| US5611078A | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | Physics | 5 | Expired |
| US7412493B2 | Publish/subscribe messaging system | Electricity | 5 | Expired |
| US8949497B2 | Method and apparatus for interleaving bursts of high-speed serial interconnect link training with bus data transactions | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.