Process for the surface treatment of semiconductor slices

US5164323A · kind A · utility

Assignee

• Wacker-Chemitronic Gesellschaft fur Elektronik Grundstoffe mbH · DE

Inventors

• Gerhard Brehm · Emmerting, DE
• Helene Prigge · Unterschleißheim, DE
• Reinhold Wahlich · Burghausen, DE

Key dates

• Filing date: Sep 12, 1990
• Grant date: Nov 17, 1992
• Expiry date: Sep 12, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3221
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor slices, in particular having the surface polished on both ss, can be provided with a surface which effects the formation of gettering centers. These centers include stacking faults and/or dislocation networks in subsequent thermal treatment steps by a pressure loading being exerted on them with the aid of an elastic pressure transmission medium which causes local pressure inhomogeneities. A material erosion, for example in the form of scratches, is not necessary in this process. Advantageously, the treatment is carried out during a template polishing step in which a suitable pressure transmission medium is in contact with the rear side of the slice. The process makes available semiconductor slices with gettering action on one side which have a high surface quality on both sides.