Via resistors within-multi-layer, 3 dimensional structures substrates
US5164699A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1990 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Dec 17, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09563
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Via resistor structures in a hybrid multilayer circuit having a plurality of insulating layers. One via resistor structure includes a plurality of resistive via fills in vias in respective adjacent insulating layers, a plurality of conductive elements for electrically contacting predetermined tops and bottoms of the resistive via fills, and conductive via fills for providing external electrical connection to selected ones of the conductive elements at locations on the outside the unitized multilayer circuit structure. A further via resistor structure includes a resistive via fill formed in a via in one of the insulating layers, and one or more thermally conductive via fills for thermally conducting heat from said resistive via fill to the outside of the unitized multilayer circuit structure. Another via resistor structure comprises ratioed via resistors comprising a plurality of resistive via fills formed in respective vias in one of the insulating layers, said vias having substantially the same thickness and having respective cross-sectional areas selected to provide resistance values having predetermined ratios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.