Distributed clock tree scheme in semiconductor packages
US5164817A · kind A · utility
18Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1991 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Aug 14, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A clock plane is embedded in the housing of a semiconductor chip package where the plane is connected to two or more clock pads on the semiconductor die through vias, bonding fingers and bonding wires. The two or more clock pads are connected by one or more clock lines. The clock plane is connected by means of a via to a clock iput pin. In this manner, a clock signal fed to the clock input pin is driven through the one or more clock line with its tributaries from two separate locations by two or more input clock pads. This reduces clock skew and permits a smaller area of the die surface to be taken up by the clock lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.