Cyclic redundancy check circuit
US5164943A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Nov 17, 1992 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.