Integrated circuit for generating a reset signal
US5166546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1992 |
| Grant date | Nov 24, 1992 |
| Priority date | — |
| Expiry date | Jan 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.