Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
US5167026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Nov 24, 1992 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decod…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.