Electroless deposition for IC fabrication
US5169680A · kind A · utility
119Cited by
11References
50Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1992 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Mar 11, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electroless deposition of a conducting material on an underlying conductive region is used in a fabrication of a semiconductor device. Electroless deposition provides a selective and an additive process for forming conductive layers, filling window and providing interconnections and terminals. The conducting material is selectively deposited on a catalytic underlying surface. When the underlying surface is not catalytic, an activation step is used to cause the surface to be catalytic. Where the base underlying surface is a substrate, a contact region is formed on the substrate for electroless deposition of the conducting material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.