MOS field-effect transistor with sidewall spacers
US5170232A · kind A · utility
38Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 4, 1991 |
| Grant date | Dec 8, 1992 |
| Priority date | — |
| Expiry date | Jun 4, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
In a n-channel MOS transistor of LDD structure with sidewall spacers, a p-type diffusion layer is formed to be on the surface of a n.sup.- drain layer just underneath the sidewall spacer and to be separated from the channel region. The low impurity concentration drain layer therefore becomes separated from the sidewall spacer, and thus degradation incident to LDD due to injection of hot carriers into the sidewall spacer can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.