Method of manufacturing integrated circuit devices
US5171711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1991 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Oct 17, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing IC devices is applied in forming bumps on an electrode pads to be an input/output terminal of the ICs with a conductive metal layer interposed therebetween. Firstly, a first resist having a prescribed opening is formed over a semiconductor substrate having the electrode pads formed thereon. Thereafter, the metal layer is formed over the semiconductor substrate, and furthermore, a second resist is formed over it by making an opening in a region almost the same as the opening of the first resist. Then, the second resist is removed after forming the bumps within the opening of the second resist. Thereafter, the first resist is removed after removing an exposed portion of the metal layer. According to the processes, overetching of and generation of an etching residue of the metal layer are prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.