Method for testing mixed scan and non-scan circuitry
US5172377A · kind A · utility
38Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1990 |
| Grant date | Dec 15, 1992 |
| Priority date | — |
| Expiry date | Sep 7, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2733
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of performing in-circuit testing of interior points of circuit boards containing both boundary-scan and non-scan components that utilizes the boundary-scan facility. The testing procedure involves isolation of the non-scan components and either driving or sensing voltages at physically accessible test sites. The method permits use of isolation and multiplexing solutions that are ordinarily developed for in-circuit testing of board components, resulting in efficient design and implementation of interconnect tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.