Digital phase lock clock generator without local oscillator
US5173617A · kind A · utility
61Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1989 |
| Grant date | Dec 22, 1992 |
| Priority date | — |
| Expiry date | Aug 10, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.