Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pins
US5175859A · kind A · utility
19Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 1990 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | May 1, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.