Avigdor Willenz
18Patents
11h-index
13Co-inventors
69Inventor score
Filing activity: May 1, 1990 → Aug 8, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5398211A | Structure and method for providing prioritized arbitration in a dual port memory | Physics | 84 | Expired |
| US5841722A | First-in, first-out (FIFO) buffer | Physics | 71 | Expired |
| US5923660A | Switching ethernet controller | Electricity | 55 | Expired |
| US5999981A | Switching ethernet controller providing packet routing | Electricity | 32 | Expired |
| US5809557A | Memory array comprised of multiple FIFO devices | Physics | 23 | Expired |
| US5586303A | Structure and method for providing a cache memory of selectable sizes | Physics | 21 | Expired |
| US5386579A | Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer | Physics | 20 | Expired |
| US5175859A | Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pins | Physics | 19 | Expired |
| US5553268A | Memory operations priority scheme for microprocessors | Physics | 15 | Expired |
| US5649232A | Structure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rate | Physics | 12 | Expired |
| US5590310A | Method and structure for data integrity in a multiple level cache system | Physics | 11 | Expired |
| USRE38821E1 | Switching ethernet controller | General | 5 | Expired |
| US5517659A | Multiplexed status and diagnostic pins in a microprocessor with on-chip caches | Physics | 5 | Expired |
| US5894176A | Flexible reset scheme supporting normal system operation, test and emulation modes | Physics | 3 | Expired |
| USRE39514E1 | Switching ethernet controller | General | 1 | Expired |
| USRE41464E1 | Switching ethernet controller providing packet routing | General | 0 | Expired |
| USRE44151E1 | Switching ethernet controller | General | 0 | Active |
| USRE43058E1 | Switching ethernet controller | General | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.