CMOS buffer circuit which is not influenced by bounce noise
US5179298A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1991 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Jan 16, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention relates to an input buffer circuit including a NOT circuit composed of N-channel MOS transistor (NMOST) and P-channel MOS transistor (PMOST). This adjusts the resistance value between the NMOST and grounding voltage VSS, or the resistance value between the PMOST and supply voltage VCC, or both resistance values so as to decrease the current flowing the supply voltage VCC to the grounding voltage VSS. According to the construction, the power consumption is suppressed, and floating of grounding voltage VSS and lowering of supply voltage VCC may be prevented, so that the switching level of the input signal will not be deviated from the target value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.