Fully planar metalization process
US5183795A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1991 |
| Grant date | Feb 2, 1993 |
| Priority date | — |
| Expiry date | Oct 10, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planar interconnect using selective, electroless deposition of a metal such as copper into interconnect channels is disclosed. A first dielectric layer is deposited on the surface of a substrate, such as an integrated circuit wafer. Thereafter, a second dielectric layer is formed on the first dielectric layer. Then a photoresist layer is spun on the top surface of the second dielectric layer. Channels are formed in the dielectric layers by patterning and etching the composite dielectric layers. Silicon atoms are implanted in the bottom of the interconnect channels and then the metal layer is selectively, electrolessly deposited to fill the channels in the first dielectric film, thus forming a level of interconnect. This process is repeated to form subsequent levels of interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.