Method of manufacturing insulated-gate type field effect transistor
US5185279A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1991 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Mar 22, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.