Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram
US5187784A · kind A · utility
20Cited by
19References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 13, 1989 |
| Grant date | Feb 16, 1993 |
| Priority date | — |
| Expiry date | Jan 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for determining the placement of circuit elements in an integrated circuit where the circuit elements are initially represented by a netlist. The method preferably includes the steps of providing predetermined ordering constraints that indicate the preferred relative locations of the circuit elements that are represented in the netlist, partitioning the circuit elements from the netlist in accordance with a predetermined balancing criterion; determining the value of a cost function associated with the partitioning steps, and selecting a particular partition based upon the value of the cost function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.