Method of producing a connection hole for a DRAM having at least three conductor layers in a self alignment manner.
US5188975A · kind A · utility
29Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1992 |
| Grant date | Feb 23, 1993 |
| Priority date | — |
| Expiry date | May 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device having at least three conductor layers, a connection hole for the lower conductor layer and the upper conductor layer can be formed in self-alignment to the intermediate conductor layer after flattening the underlying insulation film for the upper conductor layer and deterioration of the insulation withstand voltage between the upper conductor layer and the intermediate conductor layer can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.