Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
US5191224A · kind A · utility
13Cited by
14References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1990 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Dec 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.