Making staggered complementary heterostructure FET
US5192698A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1992 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Mar 17, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/072
Abstract
It is desirable to implement complementary field effect transistors in group III/group V compound semiconductors, especially on InP substrates. Outstanding n-channel performance has been demonstrated in InGaAs channel devices on InP substrates. Preliminary experiments indicate that GaAsSb channel devices will result in optimal p-heterostructure FETs (HFETs). This disclosure teaches a technique to fabricate both n- and p-channel devices on the same substrate, allowing the demonstration of (C-HFET) technology. The HFET structure contains a channel region and the barrier region. The channel region consists of two distinctive parts: the p-channel and the n-channel areas. The p-channel area consists of GaAsSb, lattice matched to the InP substrate. In n-channel FETs, and ohmic contacts are formed by first doping the contact areas with Si by ion implantation, annealing the structure and then depositing and annealing the ohmic metal. In the complementary FET p-channel FETs, BE ion implementation is used for formation of ohmic contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.