Method of making field effect transistor
US5192700A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1992 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Jan 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/824
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor including a semi-insulating semiconductor substrate, a first conductivity type semiconductor layer disposed on the substrate and forming a heterojunction with the substrate, second conductivity type spaced apart source and drain regions extending through the layer into the substrate, a metallic gate disposed on the layer between the source and drain regions, and a second conductivity type channel disposed in the substrate extending between the source and drain regions and forming a pn heterojunction with the layer for reducing leakage current from the channel to the gate. The second conductivity type channel is produced by ion implantation, and the implantation conditions are controlled as a mechanism for controllably establishing a threshold voltage for the field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.