Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol
US5193163A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1990 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Oct 1, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.