Semiconductor device of an LDD structure having a floating gate

US5194924A · kind A · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Kazuhiro Komori · Higashikurume, JP
• Kenichi Kuroda · Tokyo, JP
• June Sugiura · Musashino, JP

Key dates

• Filing date: Oct 23, 1991
• Grant date: Mar 16, 1993
• Expiry date: Oct 23, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.