Electrically programmable non-volatie semiconductor memory device
US5194925A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1991 |
| Grant date | Mar 16, 1993 |
| Priority date | — |
| Expiry date | Feb 21, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A one transistor memory cell for a flash EEPROM includes: a first control gate which is disposed on a first channel region between a source region and a drain region and separated therefrom by a first insulating film; a floating gate disposed on a second channel region and is separated therefrom by a second insulating film, the floating gate disposed on the first control gate and separated therefrom by a first interlayer insulating film; and a second control gate disposed on a surface of said floating gate and separated therefrom by a second interlayer insulating film; and wherein one end of the second control gate and one end of the first control gate are electrically connected to each other through a third control gate, thereby enhancing capacity between the control gates and the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.