Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
US5196251A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1991 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Apr 30, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes: PA0 a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate; PA0 an electrically conductive I/O pad electrically connected to at least one of the vias; PA0 an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; and PA0 a protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion. Also disclosed is a method of protecting a ceramic substrate from corrosion, the ceramic substrate of the type having a plurality of electrically conductive vias extending to a surface of the substrate, a multilayer metallic I/O pad electrically connected to at least one of the vias, and an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet, the method comprising the step of: PA0 encapsulating fully the I/O pad with a protective layer of polymeric material, wherein the layer of polymeric material protects the I/O pad from corrosion. In a preferred embodiment, the I/O pin is selectively exposed to plasma ashing to remove any err…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.