Sliced addressing multi-processor and method of operation
US5197140A · kind A · utility
209Cited by
10References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1989 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Nov 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.