Keith Balmer
70Patents
38h-index
26Co-inventors
88Inventor score
Filing activity: Dec 1, 1988 → Oct 16, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5212777A | Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation | Physics | 402 | Expired |
| US5239654A | Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode | Physics | 317 | Expired |
| US5471592A | Multi-processor with crossbar link of processors and memories and method of operation | Physics | 309 | Expired |
| US6829696B1 | Data processing system with register store/load utilizing data packing/unpacking | Physics | 289 | Expired |
| US5758195A | Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register | Physics | 259 | Expired |
| US5613146A | Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors | Physics | 241 | Expired |
| US5768609A | Reduced area of crossbar and method of operation | Physics | 231 | Expired |
| US5522083A | Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors | Physics | 228 | Expired |
| US6070003A | System and method of memory access in apparatus having plural processors and plural memories | Physics | 222 | Expired |
| US5197140A | Sliced addressing multi-processor and method of operation | Physics | 209 | Expired |
| US5696913A | Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor | Physics | 207 | Expired |
| US5226125A | Switch matrix having integrated crosspoint logic and method of operation | Physics | 186 | Expired |
| US5371896A | Multi-processor having control over synchronization of processors in mind mode and method of operation | Physics | 171 | Expired |
| US5809288A | Synchronized MIMD multi-processing system and method inhibiting instruction fetch on memory access stall | Physics | 168 | Expired |
| US6260088A | Single integrated circuit embodying a risc processor and a digital signal processor | Physics | 149 | Expired |
| US5805913A | Arithmetic logic unit with conditional register source selection | Physics | 140 | Expired |
| US6370558B1 | Long instruction word controlling plural independent processor operations | Physics | 135 | Expired |
| US5761726A | Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor | Physics | 125 | Expired |
| US6745319B1 | Microprocessor with instructions for shuffling and dealing data | Physics | 118 | Expired |
| US5590350A | Three input arithmetic logic unit with mask generator | Physics | 117 | Expired |
| US5592405A | Multiple operations employing divided arithmetic logic unit and multiple flags register | Physics | 114 | Expired |
| US5606520A | Address generator with controllable modulo power of two addressing capability | Physics | 109 | Expired |
| US5339447A | Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data | Physics | 107 | Expired |
| US6185629A | Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time | Physics | 102 | Expired |
| US5995748A | Three input arithmetic logic unit with shifter and/or mask generator | Physics | 98 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.