Trench-capacitor-one-transistor storage cell and array for dynamic random access memories
US5198995A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1990 |
| Grant date | Mar 30, 1993 |
| Priority date | — |
| Expiry date | Oct 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices. The bitlines are prevented from charging to greater than VDD--Vg, which could cause the array devices of unselected cells to conduct current and alter the stored low-voltage state of such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.