Integrated circuit with planar dielectric layer
US5200358A · kind A · utility
51Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1991 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Nov 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.