Poly sidewall process to reduce gated diode leakage
US5202279A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1990 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Dec 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.