William R. McKee
40Patents
12h-index
46Co-inventors
81Inventor score
Filing activity: Feb 7, 1977 → Mar 8, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6294420A | Integrated circuit capacitor | Electricity | 211 | Expired |
| US6096597A | Method for fabricating an integrated circuit structure | Electricity | 62 | Expired |
| US6461955B1 | Yield improvement of dual damascene fabrication through oxide filling | Electricity | 28 | Expired |
| US4430150A | Production of single crystal semiconductors | Chemistry; Metallurgy | 27 | Expired |
| US5251168A | Boundary cells for improving retention time in memory devices | Electricity | 27 | Expired |
| US4614835A | Photovoltaic solar arrays using silicon microparticles | Emerging Cross-Sectional Technologies | 26 | Expired |
| US5247254A | Data recording system incorporating flaw detection circuitry | Physics | 22 | Expired |
| US4425408A | Production of single crystal semiconductors | Emerging Cross-Sectional Technologies | 18 | Expired |
| US4413020A | Device fabrication incorporating liquid assisted laser patterning of metallization | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6396088B2 | System with meshed power and signal buses on cell array | Physics | 14 | Expired |
| US5352913A | Dynamic memory storage capacitor having reduced gated diode leakage | Electricity | 14 | Expired |
| US6528888B2 | Integrated circuit and method | Electricity | 12 | Expired |
| US5202279A | Poly sidewall process to reduce gated diode leakage | Electricity | 12 | Expired |
| USRE31473E | System for fabrication of semiconductor bodies | General | 11 | Expired |
| US6115279A | System with meshed power and signal buses on cell array | Physics | 10 | Expired |
| US6239479A | Thermal neutron shielded integrated circuits | Electricity | 10 | Expired |
| US4188177A | System for fabrication of semiconductor bodies | Chemistry; Metallurgy | 9 | Expired |
| US6653676B2 | Integrated circuit capacitor | Electricity | 9 | Expired |
| US7402514B2 | Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer | Electricity | 9 | Expired |
| US5112762A | High angle implant around top of trench to reduce gated diode leakage | Electricity | 8 | Expired |
| US4322379A | Fabrication process for semiconductor bodies | Chemistry; Metallurgy | 8 | Expired |
| US7694269B2 | Method for positioning sub-resolution assist features | Physics | 7 | Active |
| US6054732A | Single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size | Physics | 7 | Expired |
| US6100588A | Multiple level conductor wordline strapping scheme | Electricity | 7 | Expired |
| US5216265A | Integrated circuit memory devices with high angle implant around top of trench to reduce gated diode leakage | Electricity | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.