Semiconductor memory circuit
US5202854A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Sep 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory circuit includes bit lines, word lines, memory cells, transfer gates, a sense amplifier, a precharge circuit and a control section. The transfer gates between the bit lines and the sense amplifier are non-conductive during the standby state of the memory. For reading-out data from the memory cell, the transfer gates are made conductive and thereafter the potential of the word line for the memory cell to be selected is raised to its high level, so that the data stored in the memory cell is read out on the bit line. Then, after the transfer gates are made non-conductive, the sense amplifier is activated. In this way, the coupling noise occuring when the transfer gates are made conductive before the level of the word lines become high and the coupling noise occuring when the transfer gates are made non-conductive after the level of the word lines become high cancel each other and, as a result, the voltage loss in the reading out of data from the memory can be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.