DRAM with a controlled boosted voltage level shifting driver
US5202855A · kind A · utility
42Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 14, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Jan 14, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM contains both driver control logic and level shifting driver circuitry to generate a voltage boosted word-line signal. The driver control logic receives timing signals and row address information to provide timing control signals for the level shifting driver. The level shifting driver provides a voltage boosted word-line signal for a predetermined period of time in response to the timing control signals. Furthermore, the driver control logic provides control to the level shifting driver circuit to assure that transistors that drive the word-line signal are not damaged by voltage during a switching transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.