Shift register
US5202908A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Nov 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A shift register includes a plurality of alternating shifting and latching sections connected in cascade. The phases of clocks (CLK, CLKB) for driving transmission gates (10, 14) of the shifting sections advance in phase relative to the phases of clocks (CLK, CLKB1) for driving transmission gates (12, 16) of the latching sections. The ON-resistance of the transmission gates (10, 14) of the shifting sections is sufficiently larger than that of the transmission gates (12, 16) of the latching sections, so that even when both of the clocks CLK and CLKB are at H or L levels due to delay imparted by inverters included in a clock generator, data to be latched is always given priority over data to be shifted. Thus, the shift register is free of a race condition which otherwise would be caused by a phase difference between the driving clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.