Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5202973A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/376
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.